In vertical GaN power device manufacturing, electronic-grade GaN substrate polishing slurry is introduced after wire sawing, grinding, and double-sided lapping sequences on 4-inch and 6-inch HVPE-grown GaN boules. The slurry is maintained at a point-of-use colloidal silica abrasive loading of 22 wt% to 30 wt%, formulated with a KOH-stabilized pH window of 9.8–11.0 and hydrogen peroxide concentration of 1.0 vol% to 3.0 vol%. Dilution with ultrapure water is qualified at 1:1 for front-side stock removal rates of 45 nm/min to 80 nm/min on a single-side polishing platform with platen speed 60 rpm to 85 rpm, carrier speed 50 rpm to 70 rpm, and downforce 3.5 psi to 5.5 psi. Compliance for wafer geometry before and after CMP is assessed against SEMI M59 substrate specifications for total thickness variation, bow, and warp, while sub-0.3 nm Ra front-side roughness is verified by atomic force microscopy according to ISO 4287:1997 profile evaluation. Metal contamination is monitored by vapor phase decomposition–inductively coupled plasma mass spectrometry with acceptance limits of ≤ 1E10 atoms/cm² for mobile ions and transition metals, and particle counting is performed in an ISO 14644-1:2015 Class 3 cleanroom environment. Electronic/EL grade slurry certification limits transition metals at ≤ 1 ppb each, total anions at ≤ 5 ppm, and large particle counts at ≤ 100 particles/mL for a 0.5 µm threshold.

The downstream production process for vertical GaN power transistors and diodes uses the polished Ga-polar (0001) surface as a homoepitaxial template for MOCVD growth of a low-carbon drift layer, typically 6 µm to 20 µm n-type GaN, followed by selective-area p-type layers and buried regrowth. Post-CMP cleaning is executed with dilute SC-1 at NH4OH:H2O2:H2O = 1:1:5 and 60 °C to 70 °C followed by megasonic deionized-water rinse to eliminate colloidal silica residues before reactor loading. The terminal finished product types include 650 V and 1200 V vertical GaN junction barrier Schottky diodes, GaN trench MOSFETs with specific on-resistance below 0.6 mΩ·cm², and cascode-mode power switching modules. Batches exhibiting edge-exclusion polish depth variation greater than ±1.5% across the wafer have been observed on production lines to increase epi-layer threading dislocation density near wafer flats, requiring rework on the same CMP tool with recipe-adjusted slurry flow from 100 mL/min to 140 mL/min. Published data for exact slurry dilution windows on ammonothermal versus HVPE substrate blanks is limited; qualification is performed per ingot lot.

What Limits Residual Particle Adhesion on Ga-Polar Surfaces Before AlGaN/GaN HEMT Epitaxy?

In RF GaN HEMT substrate preparation, the relationship between CMP-induced subsurface damage and two-dimensional electron gas mobility requires that the final polish remove 200 nm to 500 nm of damaged GaN while producing an epi-ready surface with micro-roughness below 0.2 nm Ra as characterized by ISO 4287:1997. The slurry at point of use is diluted 1:2 with ultrapure water, with abrasive solids reduced to 18 wt% to 25 wt%, pH adjusted to 10.0–10.8, and oxidizer addition held at 0.5 vol% to 1.5 vol% hydrogen peroxide to suppress pitting on Ga-polar terraces. Platen speed is set at 70 rpm to 90 rpm, head pressure at 2.5 psi to 4.0 psi, and slurry flow at 120 mL/min to 170 mL/min. Compliance anchors to SEMI M59 for particle and metal limits and to MIL-PRF-38535 for end-device lot acceptance, while defect inspection uses dark-field laser scattering with less than 50 defect counts per wafer at 0.15 µm equivalent polystyrene latex sphere calibration. The post-CMP wet cleaning uses SC-2 at HCl:H2O2:H2O = 1:1:6 and 70 °C because residual potassium above 1E11 atoms/cm² has been associated with threshold voltage drift in accelerated test.

The downstream process consumes front-side polished GaN substrates as homoepitaxial templates in MOCVD growth of AlGaN/GaN heterostructures with an AlN interlayer of 0.5 nm to 1.5 nm, then fabricates gate trenches or field plates by electron-beam lithography. Terminal finished products include S-band and X-band MMIC power amplifiers, 5G massive MIMO base station front-end modules, and Ka-band satellite communication transceivers. In high-volume production, batch-to-batch variance in large-particle counts greater than 0.8 µm is monitored by single-particle optical sensing; any lot above 200 particles/mL is rejected before wafer loading to avoid shallow pit generation during the final buff step.

When Subsurface Damage from Ga-Polar CMP Propagates into InGaN Multi-Quantum Wells

In GaN blue and violet laser diode substrate finishing, subsurface damage from aggressive CMP propagates into InGaN multi-quantum wells as non-radiative recombination centers if the final polish fails to remove the amorphous layer generated by upstream mechanical grinding. The slurry is prepared at higher solids content—25 wt% to 35 wt% colloidal silica—with pH maintained at 11.0–11.5 using tetramethylammonium hydroxide rather than KOH to control mobile ion drift into p-side layers; oxidizer is restricted to 0.3 vol% to 1.0 vol% H2O2 to moderate the GaN etch rate and avoid step bunching on vicinal wafers with miscut 0.35° to 0.65°. Point-of-use dilution is held at 1:1, and the process runs on a rigid-polisher with in situ coefficient-of-friction monitoring, maintaining downforce 2.0 psi to 3.5 psi and platen temperature 28 °C to 35 °C. Compliance is referenced to SEMI M59 wafer geometry, Telcordia GR-468-CORE qualification for optoelectronic active devices, and ISO 14644-1:2015 Class 3 for particle limits. Device wafers with residual CMP scratch depth greater than 1.5 nm exhibit a reduction in threshold current uniformity of more than 8% across a 2-inch wafer; production lots therefore receive post-CMP cathodoluminescence screening at room temperature.

Downstream manufacturing employs the polished GaN surface for MOCVD growth of an n-AlGaN cladding layer, InGaN multiple quantum wells emitting at 405 nm to 450 nm, an electron blocking layer, and p-AlGaN cladding before ridge waveguide definition and cleaved facet formation. The terminal finished products are high-power blue-violet laser diodes for laser display, automotive white-light illumination, and industrial cutting or welding modules. Published data for exact step-bunching control on ammonothermal GaN with this slurry chemistry is limited; the absence of peroxide in the buff step has been validated only for specific ingot polarities.

Micro-LED Wafer Backside Thinning and Bonding Interface TTV Control

For micro-LED display fabrication, GaN substrate backside thinning after wafer-to-wafer bonding to a silicon CMOS backplane requires a low-stress CMP step with abrasive solids diluted 1:3 to 10 wt% to 15 wt%, pH adjusted to 9.5–10.5, and no added peroxide to avoid preferential N-face etch pit generation. The process is performed on a soft polyurethane pad with platen speed 50 rpm to 65 rpm, downforce 1.5 psi to 2.5 psi, and slurry flow 80 mL/min to 110 mL/min, targeting a final substrate thickness of 30 µm to 50 µm and total thickness variation below 1.0 µm within the bonded wafer. Compliance for wafer geometry is verified against SEMI M59 TTV and bow parameters, and the post-thinned stack is inspected with infrared transmission for bond void evolution per ISO 14644-1:2015 cleanroom protocols. The terminal products are micro-LED arrays for augmented-reality waveguides, automotive instruments, and modular video walls. Insufficient endpoint control in backside CMP has been observed on production lines to cause carrier wafer edge chipping when TTV exceeds 1.8 µm, requiring re-polish with reduced table speed.

For GaN-on-GaN photonic integrated circuits operating in the visible and near-ultraviolet range, the polish must produce not only low roughness but also minimize pit density on both Ga-polar and N-polar surfaces. The slurry is applied as a final buff at 1:4 dilution with 8 wt% to 12 wt% silica, pH 9.2–10.2, and oxidizer concentration 0.1 vol% to 0.5 vol% hydrogen peroxide to reduce CMP-induced oxygen vacancies at the waveguide sidewall interface. Platen speed is 40 rpm to 55 rpm and downforce 1.0 psi to 2.0 psi; removal is limited to 20 nm to 40 nm over a 10-minute polish to protect buried grating structures. Compliance references SEMI M59 for wafer flatness and ISO 14644-1:2015 Class 3 for defect control. Downstream production defines ridge waveguides by Cl2/BCl3 inductively coupled plasma etching, followed by SiO2/TiO2 cladding deposition and dicing of 2 × 6 mm² photonic die. Terminal products include on-chip Raman spectrometers, biosensing disposable cartridges, and free-space optical communication transmitters. Published data for CMP slurry interactions with epitaxially regrown p-GaN layers in this specific configuration is limited.