| Код ТН ВЭД | 579008 |
Как аккредитованная фабрика по полисиликонной полировке шламы электронной /EL-класса, мы соблюдаем строгие протоколы качества - каждая партия подвергается строгим испытаниям для обеспечения последовательных стандартов эффективности и безопасности.
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After LPCVD polysilicon deposition of 150–400 nm at 620–650°C on 300 mm logic wafers, the nine-point ellipsometric thickness range typically falls between 8 nm and 14 nm before any chemical mechanical planarization. That residual thickness gradient translates directly into gate etch depth bias, contact resistance spread, and drive current mismatch across the die. The EL-grade slurry is blended at point-of-use as 1 part concentrate to 1.5 parts ultrapure water, yielding a colloidal silica content of 10–12 wt% and a secondary particle size of 35–50 nm. For standard gate-first flow, oxidizer addition is omitted because 0.01–0.05 wt% hydrogen peroxide accelerates static etch of polysilicon and lowers the poly/oxide clearing selectivity. The polishing step runs on a 300 mm four-zone head CMP system with a polyurethane pad of Shore D hardness 52–58, 3.2 psi downforce, 87 rpm platen speed, 83 rpm head speed, and 200–250 mL/min slurry flow. Under these conditions the blanket polysilicon removal rate is 2,200–2,800 Å/min, while thermal oxide removal is held below 45 Å/min, giving a measured selectivity window of ≥50:1 across pad life. Pad temperature is maintained at 40–45°C; above 45°C, shear-induced agglomeration raises microscratch density and forces early pad change. Post-polish surface roughness measured by 10 μm × 10 μm atomic force microscopy remains below 0.2 nm Ra when the diamond pad conditioner sweep is set to 10–12 sweeps/min. Compliance documentation references ISO 14644-1:2015 Class 3 particle counts, REACH Regulation (EC) No 1907/2006 Annex XVII restricted substance thresholds, and RoHS Directive 2011/65/EU Annex II material bans. Terminal products from this integration route are mobile application processors, discrete graphic processors, and 5G modem SoCs.
Trench capacitor DRAM integration fills deep silicon trenches with highly doped polysilicon; after fill, the wafer surface carries 0.8–1.5 μm of polysilicon overburden above a silicon nitride collar and pad layer. The CMP process must clear this overburden without breaching the nitride, because 20–30 nm of unintended nitride loss shifts storage node recess and degrades capacitance retention. In this application the slurry is blended at 1:2 to 1:3 concentrate-to-ultrapure-water, reducing abrasive loading to 4–6 wt% and intentionally lowering the polysilicon removal rate to 900–1,400 Å/min for better endpoint control. The formulation uses 30–40 nm colloidal silica and a polycarboxylate adsorption inhibitor that suppresses nitride removal to below 40 Å/min. The resulting blanket selectivity to silicon nitride ranges from 30:1 to 60:1 depending on point-of-use pH, pad conditioning frequency, and slurry flow. Amine-based pH adjusters above 0.1 wt% must be avoided because they reverse inhibitor adsorption and create pad residue that increases nitride loss. The polishing sequence is executed on a 300 mm polisher with 2.5–3.0 psi downforce, 73 rpm platen speed, 67 rpm head speed, and 180–220 mL/min flow rate. Post-CMP nitride thickness is measured by 49-point spectroscopic ellipsometry; the within-wafer range is held to ≤10 Å. Compliance records for this memory-specific slurry grade include ISO 9001:2015, ISO 14644-1:2015 Class 3, REACH Annex XVII, and RoHS 2011/65/EU Annex II. Terminal products are DDR5 synchronous DRAM, LPDDR5X mobile DRAM, and high-bandwidth memory stacks.
| Dilution ratio (concentrate:UPW) | Point-of-use pH | Polysilicon removal rate (Å/min) | Nitride removal rate (Å/min) | Selectivity ratio |
|---|---|---|---|---|
| 1:2.0 | 10.2 | 1,400 | 35 | 40:1 |
| 1:2.5 | 10.4 | 1,100 | 28 | 39:1 |
| 1:3.0 | 10.6 | 900 | 20 | 45:1 |
For MEMS accelerometer and gyroscope production, 2–20 μm thick polysilicon structural layers deposited by LPCVD or silicon epitaxy exhibit thickness gradients and surface roughness that propagate directly into DRIE trench profile variation. The planarization step uses a diluted slurry at 1:4 concentrate-to-ultrapure-water, producing 2.5–3.0 wt% abrasive loading and a lower removal rate of 500–800 Å/min to protect thin sacrificial oxide stop layers. The colloidal silica particle size is 20–30 nm, which minimizes microscratch density on large-area springs and comb-drive structures. Polishing is performed on a 200 mm CMP tool with a stacked pad configuration—a hard polyurethane top pad over a compressible sub-pad—at 1.5–2.0 psi downforce, 60 rpm platen speed, and 120–150 mL/min slurry flow. The production sequence includes a dilute NH4OH scrub clean immediately after CMP to prevent particle adhesion on exposed oxide and metal electrodes. Acidic post-CMP chemistries must not contact the wafer before residual slurry removal because a pH drop below 4 flocculates silica and increases defect density above 0.12 defects/cm². Compliance is documented under ISO 14644-1:2015 Class 5 cleanroom operation, REACH Annex XVII, RoHS 2011/65/EU Annex II, and ISO 14001:2015 for spent slurry waste handling. Terminal products are three-axis accelerometers, MEMS gyroscopes, and six-axis inertial measurement units.
In 1200 V IGBT and 650 V power MOSFET fabrication, patterned polysilicon field plates deposited over thick field oxide create vertical steps that exceed 0.5–1.0 μm before planarization. The CMP process is designed to reduce step height to below 25 nm so that subsequent interlayer dielectric deposition does not develop voids or keyholes. The slurry is blended at 1:1 to 1:1.5 with ultrapure water, maintaining an abrasive concentration of 10–14 wt% and a secondary particle size of 50–80 nm. The high-solids formulation delivers 2,500–3,200 Å/min polysilicon removal at 3.0–3.5 psi downforce on a 200 mm or 300 mm polisher with 90 rpm platen speed and 200–260 mL/min flow. A hard polyurethane pad with low compressibility is required because the topography is dominated by large geometric steps rather than dense fine-line features. Soft pads increase bulk step-height reduction but cause oxide erosion at field plate corners, changing the electric field distribution in the final device. Endpoint is controlled by optical thickness monitoring with a target stop tolerance of ±0.5% remaining thickness. Compliance for power discrete qualification includes AEC-Q101 Rev E, REACH Annex XVII, RoHS 2011/65/EU Annex II, and ISO 14644-1:2015 Class 5. Terminal products include trench-gate IGBTs, power MOSFETs, and smart power modules.
Directly after 300 mm monitor wafers complete implant or etch qualification loops, residual polysilicon films must be stripped and re-polished before reuse to avoid cross-contamination. The reclaim CMP step dilutes the EL-grade slurry at 1:5 with ultrapure water, lowers the solids to 2.5–3.0 wt%, and still removes 2,000–2,500 Å/min of blanket polysilicon at 4.0 psi downforce on a dedicated 300 mm reclaim polisher. Because device yield is not at risk, the process tolerance is wider: the reclaimed wafer surface is qualified by 25-point ellipsometry rather than full 49-point mapping, and post-polish thickness variation is accepted at ≤30 Å. Compliance for reuse is governed by ISO 14644-1:2015 Class 6 cleanroom handling, REACH Annex XVII, and internal reclaim specifications. Terminal products are production monitor wafers, particle qualification wafers, and furnace dummy wafers.
Automotive-grade mixed-signal ICs fabricated on polysilicon gate electrodes require trace metal contamination below 1×1010 atoms/cm² for chromium, iron, nickel, and copper to prevent gate oxide integrity degradation during time-dependent dielectric breakdown testing. After the polysilicon CMP step, the wafer transfers to a megasonic cleaning module within 120 seconds to prevent silica residue from drying on the hydrophilic surface. The slurry is blended at 1:2 with ultrapure water; the point-of-use pH is held at 10.3–10.5 because excursions above 10.6 increase pad residue and reduce cleaning efficiency. The cleaning sequence uses 0.5% NH4OH and 0.1% H2O2 at 40°C, followed by 0.1% HF for 15 seconds to lift residual metal ions. Final rinsing uses ultrapure water with dissolved oxygen below 5 ppb to avoid copper redeposition. The full process is run on a 300 mm polisher with integrated cleaner, 2.8 psi downforce, 83 rpm platen speed, and 200 mL/min slurry flow. Compliance is anchored to AEC-Q100 Rev H, ISO 14644-1:2015 Class 2, REACH Annex XVII, and RoHS 2011/65/EU Annex II. Terminal products are automotive MCUs, ABS controllers, and airbag sensor interfaces.
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Polysilicon Polishing Slurry Electronic/EL Grade is an alkaline colloidal silica chemical mechanical planarization fluid formulated for selective removal of polycrystalline silicon, amorphous silicon, and silicon-germanium films in front-end semiconductor manufacturing. The product is supplied as a concentrated aqueous dispersion with abrasive solids between 1.0 wt% and 5.0 wt%, pH at 25°C controlled within 10.0–10.8, and a trace-metal ceiling of 100 ppb total alkali and transition metals. Representative model designations EL-PS-30, EL-PS-50, and EL-PS-80 correspond to primary abrasive fractions with mean particle diameters of 30 nm, 50 nm, and 80 nm as measured by dynamic light scattering in accordance with ISO 22412:2017. The grade is intended for 300 mm and 200 mm polishers used in gate and interpoly dielectric planarization, shallow trench isolation polysilicon fill, and dummy gate removal, where metallic contamination and defectivity are subject to tighter control than general-purpose polishing fluids. The alkaline dispersion is oxidizer-free; removal activity is generated by controlled silicon hydrolysis and mechanical abrasion rather than by transition-metal-catalyzed oxidation.
Particle size selection directly affects post-polish surface roughness. The EL-PS-30 model produces blanket polysilicon RMS roughness below 1.0 nm over 10 µm × 10 µm atomic force microscopy scans after 30 s over-polish, while EL-PS-80 can leave roughness up to 1.8 nm but removes material faster for thick polysilicon fill. The smaller abrasive is therefore assigned to sub-45 nm gate-length flows; the larger abrasive is acceptable for sacrificial layers and thick planarization. Surface texture is assessed according to ISO 25178 using areal roughness parameters rather than single-line profiles. The correlation between abrasive diameter and post-CMP roughness is monotonic only within the stable pH range; outside the range, agglomeration dominates and roughness increases independent of primary particle size.
Separation from general-purpose polysilicon slurry is based on three parameters rather than on a single particle-size average: cation contamination, large-particle tail, and zeta-potential stability. General-purpose slurries may tolerate total trace metal loads between 1 ppm and 5 ppm; the electronic/EL grade is released only when the individual concentrations of sodium, potassium, iron, copper, nickel, chromium, and zinc are below 50 ppb, and total metal load is below 100 ppb. Large-particle populations are controlled at the point of manufacture by depth filtration and by single-particle optical sensing calibrated per ISO 21501-4; release specifications limit particles ≥0.5 µm to ≤100 counts/mL. Zeta potential is monitored with electrophoretic light scattering and held between −20 mV and −50 mV at the natural alkaline pH; excursions toward −10 mV correspond to reduced electrostatic repulsion, higher agglomeration, and increased microscratch density on blanket polysilicon monitor wafers. On production-scale 300 mm tools, the electronic/EL grade reduces post-clean scratch adders to fewer than 10 at 0.2 µm threshold on patterned flows, while general-purpose materials may produce 20–50 adders under identical pad and conditioning conditions.
A direct substitution of an oxide CMP slurry is not appropriate where polysilicon removal selectivity is required. Oxide slurries may remove thermal oxide at 3,000–5,000 Å/min; the electronic/EL polysilicon slurry deliberately maintains oxide removal below 200 Å/min. Conversely, the polysilicon grade is not suitable for copper barrier, tungsten plug, or other metal CMP operations because those systems require acidic or peroxide-containing formulations and different abrasive chemistry.
Lot-release data are generated by closed-vessel acid digestion followed by inductively coupled plasma mass spectrometry per ISO 17294-2:2016. Sodium and potassium are limited because they migrate into gate oxides and shift threshold voltage on finished devices. Iron, copper, nickel, chromium, and zinc are limited because they catalyze decomposition of alkaline silica and create localized electrostatic defects. The release protocol includes accelerated storage at 40°C for 7 days; a mean particle size shift greater than 10% or a large-particle count exceeding 150 counts/mL after this test disqualifies the lot. Viscosity at 25°C is specified between 1.0 mPa·s and 3.0 mPa·s at 100 s−1 according to ISO 3219:2016. The D50 values are model-dependent; D90/D50 span is held below 1.8, and D99 is kept below 0.5 µm for the smallest abrasive grade. The slurry is filled under cleanroom-compatible conditions and double-bagged to reduce airborne boron or phosphorus contamination. Tests for pH use ASTM E70-19; lot-to-lot pH drift is held within ±0.2 pH of the stated target because a shift above 10.8 accelerates silicon dissolution and reduces planarization efficiency, while a shift below 10.0 lowers removal rate and may destabilize the colloidal silica.
| Property | Electronic/EL grade specification | Analytical reference |
|---|---|---|
| pH at 25°C | 10.0–10.8 | ASTM E70-19 |
| Abrasive concentration | 1.0–5.0 wt% | ISO 3251:2019 |
| Mean particle size D50 | 30–80 nm by model | ISO 22412:2017 |
| Viscosity at 25°C, 100 s−1 | 1.0–3.0 mPa·s | ISO 3219:2016 |
| Total trace metals | ≤100 ppb | ISO 17294-2:2016 |
| Large particle count ≥0.5 µm | ≤100 counts/mL | single-particle optical sensing per ISO 21501-4 |
Removal rate and selectivity are process- and equipment-dependent. On a 300 mm conformable polyurethane pad with platen speed between 80 rpm and 120 rpm, head speed between 90 rpm and 110 rpm, downforce between 1.0 psi and 4.0 psi, and slurry flow between 100 mL/min and 300 mL/min, the EL-PS-50 model typically removes blanket polysilicon at 1,800–3,200 Å/min. The removal rate on plasma-enhanced tetraethyl orthosilicate is held below 200 Å/min and on silicon nitride below 100 Å/min under the same conditions; this produces poly-to-oxide selectivity above 15:1 and poly-to-nitride selectivity above 20:1. The values are comparator ranges for process development, not guaranteed specifications, because pad type, conditioning regime, and exposure time alter local material removal. Published data for this specific configuration is limited to single-tool evaluations rather than multi-site statistical process control data.
Point-of-use handling determines whether the electronic/EL grade remains within its low-defectivity envelope. Dilution is performed with ultrapure water having resistivity of at least 18.2 MΩ·cm at 25°C and total organic carbon below 5 ppb; common dilution ratios are 1:1 to 1:4 depending on the platen geometry and desired removal rate. The diluted slurry passes through a 0.5 µm point-of-use membrane filter before entering the dispense arm. Low-shear bellows or diaphragm pumps are preferred because peristaltic pumps can generate large-particle counts above 200 counts/mL after extended recirculation. Flow rates of 100–300 mL/min are typical for 300 mm tools; flow below 80 mL/min risks pad starvation and non-uniform removal at the wafer edge, while flow above 400 mL/min wastes slurry and may alter hydroplaning behavior. Platen conditioning uses an in-situ diamond disk with grit between 100 µm and 200 µm; conditioning downforce is generally 0.5–1.5 psi. The pad is pre-conditioned for 15–30 min before the first wafer of a lot. Batch-to-batch lubricity changes are tracked by viscosity and zeta potential because a drop in zeta potential below −20 mV often precedes pad particle adhesion and defectivity increase.
Production-scale equipment behavior has shown two recurring failure modes on 300 mm slurry distribution loops. First, point-of-use filters that are not replaced after 200 L of concentrate throughput develop differential pressure above 20 psi, reducing flow and producing edge-fast removal non-uniformity. Second, storage totes that remain unagitated for more than 24 h develop a soft sediment layer; this is not hard settling because of the high negative surface charge, but it reduces top-stream solids and changes removal rate. Low-shear recirculation at 5–10 L/min rehomogenizes the dispersion within 15 min. These limits are derived from production-scale slurry distribution system evaluations rather than laboratory beaker tests.
Selective polysilicon CMP on replacement-gate modules imposes a narrow process window because over-polish into silicon nitride increases gate height erosion. The electronic/EL grade is formulated with a nitride-stop selectivity package that slows silicon nitride removal below 100 Å/min while maintaining polysilicon removal above 1,800 Å/min on a 300 mm tool with a closed-cell polyurethane pad. Endpoint detection uses optical emission or motor current; after endpoint, the over-polish step is limited to 10–20 s to avoid nitride loss. The pH is held in the lower half of the range, between 10.2 and 10.5, because higher pH raises blanket silicon nitride removal and reduces selectivity. The formulation does not contain hydrogen peroxide; addition of peroxide at point-of-use is not recommended because it shifts the silicon surface chemistry toward a more aggressive dissolution mode and may increase dishing on wide polysilicon lines. Post-polish cleaning with dilute ammonium hydroxide followed by megasonic-assisted rinse removes silica residuals without attacking the silicon nitride stop layer. The slurry is not recommended for polysilicon CMP where the underlying stop layer is amorphous carbon or where metal contamination below 10 ppb is required without additional point-of-use cation filtration.
Storage boundaries and incompatibilities are specified to preserve colloidal stability. The slurry must be stored between 5°C and 25°C; freezing causes irreversible silica aggregation and cannot be remediated by shear mixing. Unopened shelf life is 6 months from date of manufacture. Once a tote is opened and recirculated through a dispense loop, the product should be consumed within 72 h unless inert-gas blanketing and 0.5 µm recirculation filtration are applied. The slurry is incompatible with cationic organic polymers, multivalent metal salts such as ferric chloride or aluminum sulfate, and strong oxidizers; contact with these materials can collapse the electrostatic double layer and produce gelation in dispense lines. Acid waste streams must be neutralized slowly and with dilution to avoid rapid pH shock; production-scale drain lines have shown silica deposition when concentrated alkaline slurry is mixed directly with acidic waste.
The following table differentiates release-control parameters of the electronic/EL grade from those typical of conventional non-electronic polysilicon slurry. The values are control targets rather than universal market specifications.
| Control parameter | Electronic/EL grade | Non-electronic polysilicon slurry |
|---|---|---|
| Total trace metals | ≤100 ppb | 1–5 ppm |
| D90/D50 span | ≤1.8 | 2.0–3.0 |
| Large particle count ≥0.5 µm | ≤100 counts/mL | often not specified |
| Zeta potential | −20 to −50 mV | uncontrolled |
| Shelf life at 25°C | 6 months | 3–6 months |